Area-efficient high-speed 3D DWT processor architecture

Introduction: 3D discrete wavelet transform (DWT) processing is widely applied for many image and video systems, such as digital television broadcasting, seismic data collection, 3D=4D medical imaging, and telemedicine because of its potential for perfect reconstruction and its lack of blocking artefacts [1, 2]. FPGA technology has been proposed as a practical hardware solution for this task because of its low cost, highly parallel processing ability, and reconfigurability [3, 4]. There are three basic kinds of structures [5] to implement wavelet transforms: convolution-based filter bank structures, lifting factorisation-based structures, and B-spline-based structures. While the lifting structure can significantly reduce the number of multiplications and accumulations, the convolution architectures can exploit constant multiplication algorithms, such as canonical signed digit (CSD) arithmetic [5], residue number systems [6], or distributed arithmetic (DA) [7, 8]. Reference [5] shows that the convolution-based architecture for biorthogonal 9=7 wavelet transform can have a lower area cost, higher throughput, and lower power consumption compared with liftingbased structures. 3D wavelet transform is quite a challenge for FPGA implementation because of its high demands of hardware area, memory management and computing speed. Some 4D medical imaging systems even need to perform 3D wavelet transforms for multiple 3D volume images. While several 1D and 2D DWT architectures have been introduced and evaluated [4–8], very few 3D architectures have been reported. References [9, 10] report several CSD-based and Booth multiplier-based 3D DWT architectures. Among various constant multiplication algorithms, DA is reported to have advantages over other algorithms for its low area cost and low circuit complexity, and was used for 1D and 2D DWT processors [6, 7]. In this Letter, the Daubechies 9=7 coefficients were chosen as the basis for the system because Daubechies 9=7 coefficients are suitable for high-ratio compression, denoising and restoration of image and video and have been applied in the Motion JPEG standard [5]. In the following Sections, a DA-based areaefficient high-speed 3D DWT architecture is presented by exploiting the symmetry of biorthogonal 9=7 coefficients to reduce area cost further.